The present invention relates to methods for analyzing integrated circuits (ICs) during design of those ICs or during failure analysis of those ICs during development. More particularly, present invention relates to a new and improved method of automatically identifying instances of close or unacceptable signal timing skew (signal timing differences) and/or close or unacceptable timing margins (set up and hold times) that might cause or be the cause of functional problems with the IC under differing conditions of temperature, voltage and process. The first above identified invention is utilized with the present improvements in defining a logic cone or rearward extending group of only the relevant circuit components or cells of the IC which cause a particular output signal at a predetermined output signal transition time and the input signals to each relevant cell that predict the functionality of that cell in the cone, to enable the present invention to analyze those cells and their input predictors for close or unacceptable skew and margin. Analysis of the IC during design and failure analysis is facilitated.
Most modern semiconductor integrated circuits (ICs) are extremely complex in the number and interconnection of their components or cells. The complexity results from a number of trends in modern electronics. For example, the continual miniaturization of ICs allows more functional cells to be placed on the same sized chip for essentially no additional cost. The cost of an IC is generally related only to the physical size of the substrate upon which the IC is formed and not to the number of components of the IC. Therefore, the effort is to include more cells and functionality in each new IC. The trend in electronics has also been toward integrating entire systems into a single chip, or at least toward integrating larger portions of entire systems into single chips. Such ICs are called application-specific integrated circuits (ASICs) or system level integrated circuits (SLICs). Moreover, most ASICs and SLICs have multiple layers of electrical conductors formed on top of the functional elements of the substrate which connect the various components. These layers of interconnects are also sufficiently complex as to themselves be sources of function-influencing factors of the ASIC or SLIC.
Fabricating a modern, complex IC, such as an ASIC or SLIC, is also a complicated task. The fabrication involves designing the schematic circuitry by using specific cells and connecting them in certain manner, and then simulating the functionality of the schematic circuitry to determine whether the circuitry meets the functional objectives. The design and the simulation are so complex that both functions are generally performed by computer programs or tools designed for those specific purposes. For example, the circuit itself is designed by the use of a behavioral level language, which defines the all of cells in the circuit and their connectivity, and in doing so creates a file known as a netlist which describes those cells and their connectivity. A schematic viewing tool obtains information from the netlist to create a visual display of the circuit and its components. To test the functionality of the circuit, a Verilog simulation program is used. The Verilog simulation program refers to the netlist and additional information which defines the logical function and time delays and other functional factors associated with each of the cells, and develops output state change signals and output transition times for each of the cells in response to a specific input signal. The output state change signals and the output transition times for each of the cells is thereafter displayed by the use of a waveform viewing tool. The waveform viewing tool makes use of the output state change and transition time information derived from the Verilog simulation program to create a display of the waveforms existing at each of the cells in the circuit. The use of behavioral level language circuit synthesis tools and Verilog simulation tools is well-known.
To perform the simulation, the internal functional behavior of each of the cells and the interconnections of the IC are defined within the simulation program. The simulation program also takes into account external influences on the IC from certain variables, such as temperature, voltage and process. The temperature variable takes into account the temperature at which the IC is subjected. In most ICs, when the temperature increases the switching and signal propagation speed of the IC diminishes. The voltage variable relates to the level of voltage of the power applied to the IC. Voltage changes may either increase or decrease the signal switching and propagation times within an particular IC, depending upon the design of the IC. The fabrication process variable refers to signal switching and propagation times differences induced in the IC according to the processing techniques used to build or fabricate the IC. In most cases, the process variable is defined with respect to a nominal process, but slight variations in the fabrication process may result in significant faster or slower signal switching and propagation times than those resulting from nominal fabrication processes.
Many of the logic cells have characteristic performance requirements which must be met in order to achieve reliable and predictable operation. One characteristic timing requirement which applies to synchronous elements, such as flip-flops and clocked latches, is a set up and hold time. A set up time requirement relates to be relative timing between the application of a clock signal and the application of a data signal to the synchronous element. To obtain proper performance of the synchronous element, the data signal must be present and applied to the synchronous element for a certain amount of time prior to the application of the clock signal to that synchronous element. If this set up time requirement is violated, the output signal from the synchronous element is not certain or predictable. The hold time requirement is similar to the set up time requirement, except that the hold time requirement relates to the amount of time that the data signal must be applied to the synchronous element after the clock signal was applied. Again, the purpose of the hold time requirement is to assure a guaranteed and predictable response from the synchronous element. The set up and hold time requirement is frequently referred to as a xe2x80x9ctiming marginxe2x80x9d requirement. The term xe2x80x9crace conditionxe2x80x9d is sometimes used to describe a violation of a set up and hold time requirement. Obviously, race conditions are to be avoided because they are indicative of unpredictable and uncertain functionality.
Another performance characteristic relates not so much to the requirements applicable to the cells themselves, but to the functionality achieved by groups of interconnected cells. Generally speaking, the design of the IC presumes that the signals applied to each of the logic cells will occur in predetermined relationships with respect to other timing events occurring within the IC. Many logic cells require the simultaneous application of numerous signals to achieve proper functionality, and in many cases two or more of those signals must be applied within a certain time window in order for the logic cell to perform its intended to function. The predictable arrival of the signals at the logic cells is the foundation for the logic design of the IC itself. Differences or skew in the timing of the signals therefore has an important and significant impact on the functionality of the IC.
Each simulation takes into account the external variables of temperature, voltage and process. Under those conditions, the proper functionality of the IC is determined, primarily by an indication of whether an output signal or signals behave as expected in response to a selected input signal. So long as the output signal or signals behave properly, the typical simulation does not consider or evaluate timing margin or signal skew with respect to the numerous internal logic cells, all of which contribute to the output signal behavior. However, since the influences of the external variables of temperature, voltage and process are recognized as having the potential to change the output signal behavior from the IC, it is also typical to run best case and worst case simulations. A best case simulation is a selected permutation of the temperature, voltage and process variables, sometimes referred to as a xe2x80x9ccorner,xe2x80x9d where it is expected or anticipated that those variables will influence the IC to have the fastest signal generation, timing, propagation and response. A worst case simulation is a different selected permutation of the temperature, voltage and process variables which is expected or anticipated to cause the IC to have the worst signal generation, timing, propagation and response functional characteristics.
Running the best case and worst case simulations allows the circuit designer to evaluate the functionality of the IC under an anticipated range of operating conditions. If the IC functions as anticipated and expected under the best case and worst case simulations, usually no effort is made to evaluate the functionality of the internal logic cells of the IC. Some prior art simulation programs have a limited capability to evaluate timing margin. These prior art margin tools work in conjunction with a simulation program to establish a timing window for each synchronous logic cell of the IC. The timing window is used to evaluate whether the data and clock signals to that synchronous logic cell occur within the set up and hold time. So long as the data and clock signals occur within the set up and hold time window, no report is generated and no attention is directed any of the logic cells. Moreover, it is not possible to get reports on those logic cells that experience set up and hold times which are marginal or close but do not violate such timing window. Furthermore, those logic cells which experience set up and hold time violations are reported for the entire IC, and other than to report those cells with timing margin violations, the prior art timing margin tool does nothing more to assist in tracing or otherwise understanding the cause of the failure.
The acceptability of the IC under the simulated best and worst case conditions is predicated upon the simulated best and worst case conditions actually duplicating the conditions which the IC will actually experience in use. Because of the increased complexity of modern ASICs and SLICs, and certain assumptions which must necessarily be made in simulating the functionality of the cells and their interconnects, there may be a significant discrepancy between the simulated worst and best case conditions and the actual conditions which the IC may practically experience. Moreover, because of the permutational influences of the temperature, voltage and process variables, coupled with the somewhat assumptive nature of the response characteristics of components within modern complex ASICs and SLICs, particularly the response characteristics of the interconnect layers, it may questionable that the selected permutation of variables actually represents the best and worst case scenarios.
In those cases where a failure of performance is recognized in either a worst case or a best case simulation, a very tedious, time-consuming and step-by-step manual analysis of the internal logic cells is typically performed. The previous invention which is mentioned first above (Ser. No. 09/597,433) greatly simplifies the process of circuit analysis under such failure conditions, by obtaining new information from the simulation to identify and locate only the relevant logic cells which contribute to the failure. However, the previous invention is primarily useful in detecting failure conditions in the circuit, not evaluating the reliability of performance under marginal conditions.
These and other considerations have given rise to the present invention.
One aspect of the present invention relates to applying the previous invention (Ser. No. 09/597,433) in a new methodology to simulate and thereby analyze the functionality of the logic cells of the IC under marginal conditions, even when simulations of the overall functionality of the IC show proper behavior in best and worst case scenarios. In this manner, the present invention may be used as an effective circuit design tool to make it more likely that the IC will perform as intended, even conditions which may not be anticipated or selected for simulation.
Another aspect of the present invention permits the circuit designer to evaluate timing margins of the logic cells and their signals within the IC, to thereby identify tight timing margins which might give rise to race conditions. By evaluating the tight timing margins with respect to each logic cell, those signal timing situations which are close to creating a set up and hold violation may be identified, even though the tight signal timing slightly avoids a set up and hold time violation.
A further aspect of the present invention permits the circuit designer to evaluate the skew between signals at each of the logic cells of the IC, thereby identifying signal skew situations which might result in malfunctions, even when the signal skew was not great enough to cause circuit failure during simulation. By evaluating the timing margin and signal skew even under conditions of proper but marginal functionality, the circuit designer is able to identify and correct those functional considerations which may result in circuit failure under actual use conditions which were not adequately anticipated by the simulation.
Lastly, a further aspect of the present invention relates to selecting and determining conditions for simulating the behavior of an IC which more truly represent an actual worst case or best case scenario. The use of the present invention allows the IC designer to determine the permutational influence of the variables on the functionality of the IC to determine the best case and worst case scenarios. By selecting and adjusting the permutation of the variables for each best and worst case scenario, the timing margin and the signal skew can be observed. When the permutation of the variables results in the best and worst case conditions of timing margin and/or signal skew, that permutation of variables constitutes the best and worst case scenarios. Determining the actual best and worst case scenarios for simulation purposes provides an added degree of confidence that the simulation is likely to have accounted for the actual best and worst case conditions to which the IC will be subjected in actual use. Accordingly, the IC can be designed and simulated to provide a greater level of reliability and robust functionality under a variety of conditions.
To achieve these and other aspects, the present invention involves a method of deriving one of timing margin or signal skew information from relevant ones of a plurality of connected logic cells and waveforms from the logic cells of a circuit. The method makes use of a circuit simulation tool to describe input and output waveforms to and from each logic cell and a transition of the waveforms and a transition time point when the transition occurs in each waveform. The steps of the method comprise selecting the output waveform and a transition time point of the selected output waveform delivered from a selected logic cell, identifying a predictive input waveform and a transition time of the predictive input waveform to the selected logic cell which causes the transition of the output signal from the selected logic cell at the selected transition time, and identifying a predictive logic cell connected to the selected logic cell which supplies the output waveform to the selected logic cell which constitutes the predictive input waveform previously identified. At least one new repetition of these three steps is performed under circumstances where the predictive logic cell identified in a previous repetition becomes the selected logic cell for the new repetition and the transition time point of the predictive input waveform to the selected logic cell of the previous repetition becomes the selected transition time of the output waveform of the selected logic cell for the new repetition. The repetitions define a logic cone formed from each of the logic cells selected and identified by performing the repetitions. The magnitudes for variables influencing the performance of the circuit under best case circumstances and worst case circumstances are thereafter selected. A first and a second instance of the logic cone is defined by using best case and worst case variable magnitudes. Timing margin or signal skew information is derived from the difference in transition times of the predictive input waveforms from the first and second instances of the defined logic cone.
Other preferred aspects and steps of the method of the present invention relate to displaying a schematic diagram of the selected and predictive logic cells identified from all of the repetitions, and displaying the input and output waveforms of the selected and predictive logic cells identified from the all of the repetitions, preferably by using a conventional schematic viewing tool and a conventional waveform viewing tool.
The method also preferably involves deriving the timing margin information of a synchronous cell which has a predictive data input waveform and a predictive clock input waveform, by determining the transition time of a selected predictive data input waveform to the synchronous cell, determining the transition time of the selected predictive clock input waveform to the synchronous cell, and determining the timing margin information for the synchronous cell from the difference in the transition times of the selected predictive data and clock input waveforms. Such timing margin information is preferably derived separately for each of the best case and worst case instances.
Another preferable aspect of the invention involves deriving the signal skew information of a selected logic cell in the best and worst case performance instances of the defined logic cone. The transition time of a selected predictive input waveform of the selected cell is determined for the best case and for the worst case, and any difference in the determined transition times is the signal skew caused by best case and worst case performance differences.
The variables and their magnitude influence the occurrence of the predictive input waveform and the transition time of the output waveform for each logic cell, and selecting the variable magnitudes preferably involves selecting different variable performance information for the best and worst cases. The variable performance information relates to temperature of the circuit, magnitude of voltage applied to the circuit, and a semiconductor fabrication process used to manufacture the circuit. In general this variable performance information describes a time delay associated with each logic cell and the interconnect conductors extending between logic cells.
Further preferred features of the method identify the predictive input waveform as a synchronous waveform, such as a clock waveform. As a part of defining a cone of connected predictive and selected logic cells by performing the repetitions, the cone may include a sub-part which involves a synchronous logic cell which causes a synchronous waveform. In such a case, the the same type of repetitions are performed to define the sub-part of the cone.
The timing margin and signal skew of the cells of a cone of logic cells is determined by using the input predictor signal, the input predictor signal transition time, the output state change signal and the output state change signal transition time. This information identifies the relevant ones or a cone of logic cells which are responsible for causing the output waveform transition at the selected time. The schematic and waveform viewing tools utilize this information to assemble the relevant schematic diagrams and waveform simulations. This assembled information facilitates a rapid and clear understanding of the functionality of the relevant logic cells under the best case and worst case timing margin and signal skew situations. The timing margin and signal skew information is available for all the cells within the logic cone. The timing margin and signal skew information is readily available to facilitate a complete understanding of the performance of the circuit, even under conditions where a failure or malfunction is not indicated by the simulation tool.
A more complete appreciation of the present invention and its scope may be obtained from the accompanying drawings, which are briefly summarized below, from the following detailed descriptions of presently preferred embodiments of the invention, and from the appended claims.